1) Field of the Invention
The present invention relates to an automatic floor-planning method for efficiently determining a floor plan for a circuit arrangement in a semiconductor (IC) unit.
2) Description of the Related Art
In recent years, with the advancement of technology of scaling-down to micro, there is a tendency to increase the number of cells that can be installed in one chip. With an increase in the number of cells, a layout design of a semiconductor IC unit, which is called as a floor plan, is getting more and more complicated and gaining importance. Therefore, it is desirable that the floor plan of the semiconductor IC unit is made easily in short time thereby shortening the period of time for designing the semiconductor IC unit.
In the designing of the semiconductor IC unit, floor planning is performed after finishing logic designing. In a conventional method of determining the floor plan, to start with, an area on a chip is determined for each logic level block and a method of level designing in which the logic level blocks are designed in respective areas, is adopted.
In such a method of level designing, a computer is allowed to read circuit-connection information and library data. The circuit-connection information includes information, in which information of logic level block and information of connection between cell terminals are defined. The information of logic level block is information of level blocks that include sets of cells. The library data includes information such as chip-substrate information and cell-structure information. The chip-substrate information includes information of silicon substrate on which the semiconductor IC unit is formed. The cell-structure information includes information of cell structure etc. about physical structure (size, shape) of the cell. After reading the library data, a designer selects a logic level block for which the floor planning is to be performed and determines an arrangement and wiring area (layout area) of the logic level block that is selected.
Arrangement of cells and wiring between the terminals of the cells are performed in the arrangement and wiring area of the logic level block. Further, simulation (testing of circuit operation) is carried out based on the final arrangement and wiring, and the floor planning is performed repeatedly to revise the arrangement and the wiring area, whenever there is a delay.
However, since the designer determines the arrangement and wiring area of the level block in such a method of determining the floor plan, depending on the simulation results, the floor plan has to be re-executed quite a few times and the designing takes longer time. To shorten the designing time, it is desirable that the re-execution of the arrangement and wiring area of the level block is reduced by making the floor plan easy.
In a method of determining the floor plan according to Japanese Patent Laid-open Publication No. H6-204437, first of all, grouping is carried out for each of those cells which realize the same function. Further, wiring between the groups is determined virtually and simulation of function is performed based on the wiring between the groups. Driving cells with insufficient driving capability are changed. Thus, the re-execution (frequency of arrangement and wiring) of the floor plan is reduced.
However, according the conventional technology, when the driving capability of the driving cells is insufficient, for changing the driving cells before the logic simulation, a large number of driving cells are required to be changed. Moreover, only changing the driving cells is not sufficient to reduce the frequency of re-execution of the floor plan.